1. Field of the Invention
This invention relates to a method of fabricating a non-volatile semiconductor memory which has a floating gate electrode and a control gate electrode and performs a tunnel injection and erasure through a local thin oxide area.
2. Description of the Related Art
As an electrically erasable programmable read-only memory (EEPROM) having a floating gate electrode and a control gate electrode, there has heretofore been known a non-volatile memory of a type wherein electrons are transferred between a floating gate electrode and a diffusion layer under a tunneling phenomenon through a thin gate oxide (tunnel oxide) opened or cut over the diffusion layer, whereby data is rewritten into another. A method of fabricating the above-described EEPROM will be described with reference to FIG. 1. As shown in FIG. 1A, a device isolation region is formed over a P-type silicon (Si) substrate 101 by LOCOS. Thereafter, an silicon oxide 102 is formed in a thickness of 200 .ANG., for example and arsenic (As) ion or the like is iimplanted to form a source and drain of an EEPROM memory cell with a resist 103 as a mask. After the oxide 102 has been removed, a gate oxide (silicon oxide) 106 is next formed in a thickness of 500 .ANG., for example, as shown in FIG. 1B. When a high voltage is applied to the gate oxide 106 to rewrite data into another through a gate oxide, it is necessary to form the gate oxide 106 to a thickness enough to prevent current from flowing. Afterwards, an opening is defined in a area of the gate oxide 106 on a drain diffusion layer 104 as shown in FIG. 1C. The opening will be called "tunnel window". The size of an open diameter of the tunnel window is of importance to a coupling ratio as will be described later.
After the removal of the resist 107, a tunnel oxide 108 is next formed within the tunnel window so as to have a thickness of 100 .ANG., for example by thermal oxidation as shown in FIG. 1D.
Thereafter, polycrystalline silicon 109, which serves as a floating gate electrode, is deposited as shown in FIGS. 2A through 2D. Afterwards, the polycrystalline silicon is etched with a resist 110 as a mask. Subsequently to its etching, an interlayer insulating film 111 is formed so as to have a thickness of 200 .ANG., for example and thereafter polycrystalline silicon 112 which serves as a control gate electrode, is formed and subjected to patterning, whereby each memory cell electrode for the EEPROM is formed.
Although, however, the conventional disclosed method has shown the case in which the current is fed through the tunnel oxide 108 100 .ANG. thick, for example, to discharge an electrical charge from the floating gate electrode 109 or charge it therein, whereby data is renewed or rewritten into another, an effective voltage applied to the tunnel oxide needs 10V or higher when the tunnel oxide 108 is 100 .ANG. thick. This case will present a problem of at what rate the voltage applied between the control gate electrode 112 and the drain 104 effectively reaches a voltage applied between the floating gate electrode 109 and the drain 104. This rate is called "coupling ratio", which is determined by the ratio of the capacitance between the control gate electrode and the floating gate electrode to the capacitance between the floating gate electrode and the drain.
As the capacitance value between the floating gate electrode and the drain is relatively small, the coupling ratio improves and the voltage which should be applied between the control gate electrode and the drain, may be low. Since the minimum value of the open diameter of the tunnel window is usually determined according to a design rule when the tunnel window is opened, the coupling ratio cannot be increased unless a memory cell is made great in particular. It was eventually necessary to apply a voltage near 20V between the control gate electrode and the drain. The need for application of such a high voltage will cause a problem in that in an LSI supplied with a normal power supply voltage of 5V or less, a gate oxide for each transistor of a peripheral circuit for driving a memory cell is made thick in thickness, the area thereof increases with its increase in thickness and the speeding down of circuit operation occurs. Since the diameter of the tunnel window cannot be set to the minimum value or less based on the design rule, the memory cell itself was accompanied by a drawback that it would increase in size to ensure allowance for alignment displacements and the coupling ratio.